Epitaxial silicon wafers for power MOS transistors, for instance, is required to have extremely low substrate resistivity. In order to sufficiently lower the substrate resistivity of silicon wafers, it is known to dope molten silicon with an n-type dopant for resistivity adjustment (e.g. arsenic (As) and antimony (Sb)) during pull-up step (i.e. in growing silicon crystal) of a single crystal ingot (referred to as a “single crystal” hereinafter) for providing silicon wafers. However, since such dopants are extremely volatile, it is difficult to sufficiently increase the dopant concentration in the silicon crystals. Thus, silicon wafers exhibiting desired sufficiently low resistivity is difficult to be manufactured.
Accordingly, silicon wafers with extremely low substrate resistivity have come to be used, in which phosphorus (P) as an n-type dopant that is less volatile than arsenic (As) and antimony (Sb) is densely doped.
On the other hand, since epitaxial growth occurs on an epitaxial silicon wafer at a high temperature, oxygen precipitates (BMD) or oxygen precipitation nuclei formed in the crystal while growing the single crystal are dissipated by the high temperature heat treatment, thereby lowering gettering ability.
In order to overcome the shortage in gettering ability, it is known to apply a polysilicon back-seal (PBS) before the epitaxial growth. The polysilicon back seal method is a kind of EG (External Gettering), in which a polysilicon film is formed on a backside of a silicon wafer to make use of strain fields or lattice mismatch created at an interface between the polysilicon film and the silicon wafer.
It is found that, however, when a polysilicon film is grown on a backside of a silicon wafer, a number of stacking faults (abbreviated as “SF” hereinafter) are generated on the epitaxial film, the SF appearing on a top side of the silicon wafer in a form of steps to significantly deteriorate LPD (Light Point Defect) level on the top side of the silicon wafer.
Accordingly, studies have been made in order to restrain the above disadvantage (see, for instance, Patent Literature 1).
Patent Literature 1 discloses that the generation of SF can be effectively restrained by forming a polysilicon film on a backside of a silicon wafer at a temperature less than 600 degrees C.